This invention relates to active matrix devices and more particularly, but not exclusively, to active matrix liquid crystal displays (AMLCDs). It is concerned with reduction of the power consumption of such devices.
Active matrix devices, such as AMLCDs, are used in a wide variety of products, including consumer electronics, computers and communication devices. The structure of an AMLCD is described for example in U.S. Pat. No. 5,130,829 (our ref PHB 33646), the contents of which are incorporated herein as reference material. Active matrix devices are often included in portable products where the minimisation of power consumption is a particularly important consideration.
AMLCDs comprise an array of pixel elements addressed by means of row and column electrodes. The row electrodes are driven with row selection signals, while the column electrodes carry video information. A significant component of the power consumption of an AMLCD is the power required to charge and discharge the columns of the display as the video information is applied to successive rows of pixels. The invention seeks to reduce the power consumed by this process.
The present invention provides an active matrix device comprising two or more adjacent sub-matrices, each comprising a set of row address conductors, a set of column address conductors, and control elements disposed at intersections of the row and column address conductors, each control element having a scan input connected to a row address conductor and a data input connected to a column address conductor, the device including row driving circuitry for applying selection signals to the row address conductors, and column address circuitry for applying data signals to the column address conductors, wherein the device is divided into sub-matrices between adjacent row address conductors, and the row driving circuitry and column address circuitry are adapted to address a control element in two or more sub-matrices simultaneously. The time taken to charge each column address conductor can therefore be increased. This reduces the frequency of the drive waveforms required to drive the device, and therefore the power consumption of the device. In a preferred embodiment, a control element in each of the sub-matrices is addressed simultaneously.
Preferably, the row driving circuitry is adapted to select a row in each sub-matrix simultaneously, and the column address circuitry is operable to apply a data signal simultaneously to a column address conductor of each sub-matrix. The row driving circuitry itself may select individually a row in each sub-matrix simultaneously, or alternatively, a row in one sub-matrix may be connected to a row in each of the other sub-matrices such that the connected rows are simultaneously selectable.
The row driving circuitry may be operable to simultaneously select rows in two adjacent sub-matrices in sequence from the adjacent to the distant edges of both sub-matrices, or vice versa. Rather than addressing the rows in each sub-matrix from top to bottom in turn, it may be advantageous to address the rows in a different sequence. If they are addressed in the same sequence then the last row to be addressed in one sub-matrix will be adjacent to the first row to be addressed in the matrix below it. There will then be a significant difference in the timing of the control element drive waveforms present in these two rows, which in display applications might result in a discontinuity in the visual appearance of the display at the junctions between the matrices. This may be avoided by addressing the first matrix from top to bottom, the second from bottom to top, the third from top to bottom, and so on.
In a preferred embodiment, the column address circuitry comprises a data supply means for each sub-matrix, and column driver means for selectively connecting the column address conductors of each sub-matrix to the respective data supply means to apply the corresponding data signals thereto.
Instead of addressing each column in a sub-matrix in turn, it may be preferable to drive each sub-matrix such that several columns are addressed simultaneously. This may allow the charging time for each column to be increased further, thus reducing the power consumption of the device. For example, each data supply means may be connected to a plurality of parallel data lines. Alternatively, the column driver means may receive data in a digital form and store the data for each column, in a latch for example. A digital to analogue converter may then be used to generate an analogue signal for application to the respective column. In that case, several or all the columns in each sub-matrix could be charged simultaneously.
The column address conductors of at least one sub-matrix may be connected to the respective data supply means via their ends adjacent another sub-matrix. Accordingly, in a device comprising three sub-matrices for example, the column address conductors of the middle sub-matrix are driveable from an edge of the sub-matrix which is adjacent one of the other sub-matrices. Conventionally, the address conductors of an active matrix are connected to driving circuitry at the outer edges of the matrix only. The column address conductors of the at least one sub-matrix may be connected to the respective data supply means by a data supply line which extends between the at least one sub-matrix and an adjacent sub-matrix.
In another embodiment, the data supply lines may be located within the respective sub-matrix, rather than at one edge. In a further preferred arrangement, the data supply lines is/are provided beneath the corresponding sub-matrix, for example, underneath one or more of the rows of control elements. It will be appreciated that the data supply lines could be provided at any vertical position within a sub-matrix, as the connections to the column electrodes may be made at any point along the length of the electrodes.
The column driver means preferably comprises a set of control lines, each control line being connected to a respective switching means in each sub-matrix, each switching means being arranged to connect selectively a column address conductor in each sub-matrix to the respective data supply means. Alternatively, the required control signals may be generated by circuitry within the column address circuitry of each sub-matrix, without requiring the inclusion of additional control lines.